On Monday, 2023-08-14 at 13:28:52 UTC, Parav Pandit wrote:
>> From: David Edmondson <>
>> Sent: Monday, August 14, 2023 6:40 PM
>
>> >> > +5. The device should be able to zero pad the header buffer when the
>> received
>> >> > + header is shorter than cpu cache line size.
>> >>
>> >> What's the use case for this (item 5)?
>> >
>> > Without zero padding, each header write results in a
>> > read-modify-write, possibly over PCIe. That can significantly depress
>> > throughput.
>>
>> Understood. So it could be anything padding, we just want to write a full cache
>> line.
> Yes. if the data descriptor is partial, need to zero fill too.
> I will double check if I covered already or not.
Perhaps the requirement, then, should be that the device is permitted
(and encouraged) to write full cache lines, with an aside that zero
padding should be used to achieve this.
--
No proper time of day.
