> From: Satananda Burla <>
> Sent: Friday, August 11, 2023 12:35 AM
> > +6. Ability to zero pad the transmit completion when the transmit
> > completion is
> > + shorter than the CPU cache line size.
> Did you mean that the last completion in a cache line will be padded ?
> For ex if a transmit completion is 16 byte, you could fit 4 of them into a
> cacheline. But if device has got only 3 completions to post, it would post
> 3 and pad the last 16 bytes.
Right. Device can choose to pad last in above example.
If 2 completions are written, it can still choose to pad remaining 2.
> I hope you did not mean that every transmit
> completion is padded to cacheline size.
Right, I didn't mean that.
David had better wording to describe this. So I will use his suggestion.
