On Thu, Oct 12, 2023 at 7:37âPM Parav Pandit <> wrote:>
> As Michael said, software based nesting is used..
I've pointed out in another thread when hardware has less abstraction
level than nesting, trap/emulation is a must.
> See if actual hw based devices can implement it or not. Many components of cpu cannot do N level nesting either, but may be virtio can.
> I donât know how yet.
I would not repeat the lessons given by Gerald J. Popek and Robert P.
Goldberg[1] in 1976, but I think you miss a lot of fundamental things
in the methodology of virtualization. For example, nesting is a very
important criteria to examine whether an architecture is well designed
for virtualization.
That is to say for any CPU/hypervisor vendors, the architecture should
be designed to run any levels of nesting instead of just an awkward 2
levels (but what you proposed can not work for even 2). For x86 and
KVM, any level of nesting has been done for about 10 years ago.
For virtio, it can do any level. So did for vhost/vDPA. For example, I
usually develop and test virtio/vDPA/vhost in a nesting environment.
Thanks
[1] https://dl.acm.org/doi/pdf/10.1145/361011.361073
